1. Field of the Invention
Apparatuses consistent with the present invention relate to a semiconductor device, and more particularly, to a semiconductor device used for a wafer-level CSP or the like that requires no wiring board (e.g., interposer).
2. Description of Related Art
In most related art semiconductor devices, a package structure in which a semiconductor chip is sealed by resin and metal leads arranged on side surfaces in the vicinity of the sealing resin, is used. However, in this package structure, the area of the package becomes larger than that of the semiconductor chip. Therefore, in recent years, a package structure called CSP (chip-scale package/chip-size package) has become widely used.
In the CSP, a ball grid array (BGA) technique is employed in which electrodes are flatly arranged on a flat surface of a package. The BGA technique allows semiconductor chips each having the same number of electrode terminals and the same projected area as those of conventional chips to be mounted on an electronic circuit board in a smaller area with high integration density. Since the area of the package is nearly the same as that of the semiconductor chip, the CSP can largely contribute to the development of small, lightweight electronic equipment.
A silicon wafer having wiring thereon is diced into semiconductor chips, and the chips are then individually packaged to form CSP chips. A package structure called a wafer-level CSP includes, on a silicon wafer, an insulating layer, a rewiring layer (i.e., conductive layer), a sealing layer, solder bumps (i.e., terminals), or the like. In the final process of fabrication, the wafer is diced into chips of a predetermined size such that the area of the package is nearly the same as that of the semiconductor chip (see Japanese Unexamined Patent Application, Publication No. 2004-207368).
In the thus-structured CSPs, the rewiring layer is kept insulated by the insulating layer and the sealing layer formed on almost entire of the substrate, such as a silicon wafer. However, the insulating layer and the sealing layer are usually formed of resin. Since resin layers can contract during curing, or undergo elastic deformation when heated, stress is generated between the insulating layer and the sealing layer, and the substrate. Such stress may cause curvature of the substrate or separation of the insulating layer and the sealing layer from the substrate. To address such a problem, Japanese Unexamined Patent Application, Publication No. 2000-353716 discloses a semiconductor device in which the insulating layer and the sealing layer are divided into sections by grooves for each terminal (i.e., bump) that is to be exposed, thereby reducing curvature in the substrate.
In the above-disclosed semiconductor device, however, since only narrow grooves are formed on the insulating layer and the sealing layer, elastic deformation of these layers cannot be absorbed completely, and thus curvature of the substrate cannot be prevented completely. In addition, since the exposed terminals (i.e., bumps) are divided only by narrow grooves, the terminals which are highly integrated may become short-circuited to one another.